1. Field of the Invention
The present invention relates to a read-only memory capable of electrically writing and erasing information and more particularly, to an improvement of a so-called EEPROM (Electrically Erasable and Programmable Read-Only Memory), enabling EEPROM to be powered by a single supply voltage and to have an improved endurance.
2. Description of the Prior Art
FIG. 1 is a diagram showing a schematic structure of a memory portion of a conventional nonvolatile semiconductor memory device and the relation between voltages applied to an electrode of each memory device at the time of data write cycle, which is, for example, disclosed in "A 128K Flash EEPROM Using Double Polysilicon Technology" by G. Samachisa, 1987 IEEE ISSS Digest of Technical Papers, pp. 76-77.
In FIG. 1, four memory transistors Q5 to Q8 are illustrated. Each of the memory transistors Q5 to Q8 comprises a floating gate for storing charges and a control gate for controlling, for example, injection/emission of charges to from the floating gate, and stores information in a nonvolatile manner. Each of the memory transistors Q5 to Q8 has a control gate formed to extend to a source region. Each of the memory transistors Q5 and Q7 has a control gate connected to a word line 25, and each of the memory transistors Q6 and Q8 has a control gate connected to a word line 26. Each of the memory transistors Q5 and Q6 has a drain connected to a bit line 22, and each of the memory transistors Q7 and Q8 has a drain connected to a bit line 23. Each of the memory transistors Q5 and Q7 has a source connected to a source line 24a, and each of the memory transistors Q6 and Q8 has a source connected to a source line 24b.
FIG. 2 is a cross-sectional view showing a schematic structure of the memory transistor shown in FIG. 1. In FIG. 2, the memory transistor comprises a drain region 33 and a source region 34 formed in a predetermined region on the surface of a semiconductor substrate 35 by implanting and diffusing impurities, a floating gate 31 formed on an insulating film 32 for a part of the floating gate to overlap with the drain region 33, and a control gate 30 formed on the floating gate 31 to extend from the drain region 33 to the source region 34. The floating gate 31 is made to be electrically floating. The insulating film 32 is formed of a thin oxide film having a thickness of about 200 .ANG.. In FIG. 2, a drain electrode 27, a control gate electrode 28 and a source electrode 29 are connected to a bit line, a word line and a source line, respectively. Referring now to FIGS. 1 and 2, description is made on operation for writing data in a conventional memory.
Data writing in the nonvolatile semiconductor memory device having the structure shown in FIG. 1 comprises an erase cycle and a program cycle. More specifically, information "1" is written to all the memory devices in the erase cycle and then, information "0" is written to the memory device to be programmed in the program cycle. Description is now made on operation at the time of the erase cycle. In the erase cycle, a program high-voltage V.sub.pp (about 20 to 25 V) is applied to all the bit lines 22 and 23 and at the same time, a ground potential 0 V is applied to all the word lines 25 and 26. Therefore, a high electric field is produced between the floating gate 31 and the drain 33 as shown in FIG. 2. The high electric field causes electrons stored in the floating gate 31 to be emitted to the drain 33 through the thin oxide film 32 by a tunnel phenomenon, as is shown by dotted arrow B in FIG. 2. In this state, the floating gate 31 is to be in a depletion state of electrons, so that the threshold voltage of the memory transistor with reference to the control gate 30 becomes lower than that before erase operation. This state is referred to as an erased state, in which a memory device stores logic "1". More specifically, after completion of the erase cycle, all the memory devices store information "1".
Description is now made of an operation at the time of the program cycle. A method of programming is the same as that in an EPROM capable of erasure by ultraviolet rays. That is, the selected bit line 23 is forced to the program high-voltage V.sub.pp, the non-selected bit line 22 is forced to the ground potential 0 V, the selected word line is forced to the program high-voltage V.sub.pp, and the non-selected word line 26 and the source lines 24a and 24b are forced to the ground potential 0 V. More specifically, in this state, programming to the memory transistor Q7 is performed, so that the high-voltage V.sub.pp is applied to the word line 25 and the bit line 23 connected to the selected memory transistor Q7. In this state, hot electrons are produced in the vicinity of the drain 33 of the transistor Q7. The produced hot electrons are accelerated by the high-voltage V.sub.pp applied to the control gate 30 to be injected into the floating gate 21, as is shown by the dotted line A in FIG. 2. As a result, the floating gate 21 stores a larger number of electrons than before, and the threshold voltage of the memory transistor Q7 with reference to the control gate 30 becomes higher than that before program operation. The state is referred to as a program state, where logic "0" is stored.
In the above described conventional nonvolatile semiconductor memory device, a single transistor can constitute a memory cell, the chip area can be reduced. However, since programming of the memory cell is performed by injection of hot electrons, a high-voltage generator circuit using an on-chip charge pump and the like does not provide sufficient current driving ability, so that the programming high-voltage must be externally applied. Therefore, the semiconductor memory device can not be operated by a single power supply of 5 V. In addition, since programming is performed by injection of hot electrons, the characteristics of the insulating film formed between the floating gate and the drain region are liable to deteriorate, and the number of times of repeating erasing/programming is as small as about 10.sup.3 times. This deterioration occurs for the following reason. The energy of hot electrons injected into the oxide (insulating film) is higher than that of electrons injected through tunneling. While the energy of a hot electron is higher than the barrier height of Si-SiO.sub.2 (the semiconductor substrate--the insulating film) interface, a tunneled electron's energy is lower than the barrier height. Therefore, the damage to the oxide (insulating film) by hot electron is much larger than that by tunneled electron.
In a structure of the conventional EEPROM in which, two transistors constitute a single memory cell, and since, in order to reduce the chip area in these devices, a control transistor CT is provided for one-byte memory cells as shown in FIG. 3 so that erasing is simultaneously performed on every one-byte memory cell, the erase cycle is necessarily required in the data write cycle.
More specifically, in the structure of the EEPROM shown in FIG. 3, the identical voltage is simultaneously applied to control gates of memory transistors MT1 to MT8 through the control transistor CT. Therefore, if it is desired to write, for example, information "0" to only a single memory cell, other memory cells can not be erased simultaneously, so that it is necessary to erase information of the one-byte memory cells so that information "1" can be stored and then, to write information "0". As a result, the erase cycle is necessarily required in the data write cycle, so that the data write cycle becomes longer.
As the prior art, a nonvolatile semiconductor memory device in which erasing is performed by a tunnel current and programming is performed by avalanche injection of electrons is disclosed in, "A 128K/EEPROM using Double Polysilicon Technology", ISSCC' 87, Digest of Technical Papers, p. 76, "A 1.5 V Single-Supply One-Transistor CMOS EEPROM", IEEE, Journal of Solid-State Circuits, Vol. SC-16, 1981, pp. 195-199, "An 8192-Bit Electrically Alterable ROM Employing a One-Transistor with Floating Gate" IEEE, Journal of Solid-State Circuits, Vol. SC-12, No. 5, 1977, pp. 507-514, "A Single Transistor Electrically Alterable Cell," IEEE Electron Device Letters, Vol. EDL-6, No. 10, October 1985, pp. 519-521, "A Source-Side Injection Erasable Programmable Read-Only-Memory (SI-EPROM) Device," IEEE Electron Device Letter, Vol. EDL-7, No. 9, September 1986, pp. 540-542, "A true Single-Transistor Oxide-Nitride-Oxide EEPROM Device," IEEE Electron Device Letters Vol. EDL-8, No. 3, March 1987, pp. 93-95, and "Electrically Erasable and Reprogrammable Read-Only-Memory Using n-channel SIMOS One-Transistor Cell," IEEE TRANSACTIONS ON Electron Devices, Vol. ED-24, No. 5, May 1977, pp. 606-610. According to the prior art, a single transistor constitutes a single memory cell but an erase cycle is included in a data write cycle, so that erasing can not be performed on a bit by a bit.